1. Field of the Invention
The present invention relates to an information processing system for processing data and instruction words, and more particularly to an information processing system which employs a high speed buffer storage and an advanced control technique.
2. Decsription of the Prior Art
As is well known, in an information processing system, particularly of large scale, the adoption of a high speed buffer storage for storing copies of data and instruction words in a main storage and the adoption of prefetch of the instructions and data are commonly used in order to enhance the processing speed. Through these techniques, the data and instruction words required in the processing are prefetched to the high speed buffer storage to enable high speed processing. However, when an instruction stream to be processed is changed by a branch instruction, the instruction words and data which are not necessary for the processing would have been prefetched in the high speed buffer storage. This is a particular problem in an information processing system having a high degree of advanced control such as in a pipeline control system. The outline of the pipeline control system and problems thereof are discussed in an article "Pipeline Architecture" by C. V. Ramamoorthy in ACM Computing Surveys, Vol. 9, No. 1, pp 61-102, Copyright 1977, Association for Computing Machinery Inc. In such an information processing system, controls are made even before a determination of a conditional branch instruction. Namely, some of the instructions and data necessary for processing both instruction streams following after the conditional branch instruction are read out of the high-speed buffer storage and sent to an instruction control unit and an arithmetic unit, respectively. Those units, however, only hold the instructions and the data until a result of the determination for the condition is made. After the result, instructions or data only corresponding to either instruction stream decided to be executed are executed or processed.
If the high-speed buffer storage does not have the instructions or the data necessary for the above instruction streams following after the conditional branch instruction, they will be read out of the main memory and transferred to the high-speed buffer storage. In this case, after the result of the determination of the conditional branch instruction, the instructions and the data for instruction streams decided not to be executed are unnecessary. Similarly, the above transfer of these unnecessary instructions and data is also unnecessary. This causes therefore a reduction of the probability of necessary instruction words and data in the buffer storage and may result in loss of instruction words and data to be used in the next step from the buffer storage.
In order to resolve the above problem, it has been proposed to suppress the initiation of the transfer stage for the instruction words and data from the main storage to the high speed buffer storage upon decoding of the branch instruction until the determination of the branch instruction, and it is determined whether the transfer stage for the main storage should be initiated or not. See Japanese Patent Application Kokai (Laid Open) No. 40824/76. In this system, fetching of unnecessary instructions words and data into the high speed buffer storage, that is, the initiation of the data transfer stage of unnecessary information from the main storage to the high speed buffer storage, is prevented. However, in this system, the advanced control for the instruction streams following the conditional branch instruction must pause until the result of the determination if the buffer storage does not have the data and/or instruction words.